1. Field of the Invention
The present invention relates to a current control circuit, class AB operational amplifier (OP) system and current control method, and more particularly, to a current control circuit, class AB OP system and current control method capable of determining an operating status according to an output voltage, to switch a bias current.
2. Description of the Prior Art
An output stage quiescent current relates to an output stage current when no signal is inputted into an operational amplifier, and is generally maintained at a specific multiple of a bias current. For an example of this, please refer to FIG. 1, which is a schematic diagram of a class AB operational amplifier 10 in the prior art. The class AB OP 10 includes input terminals Vin−, Vin+, an output stage 9, transistors M9˜M16 and current sources 102, 104. The M15, M16 transistors relate to an output stage with an output stage quiescent current IQ. The current sources 102, 104 provide bias currents IB2, IB3, respectively. In short, a sum of a gate-to-source voltage Vgs11 of the transistor M11 and a gate-to-source voltage Vgs12 of the transistor M12 is equal to a sum of the gate-to-source voltage Vgs15 of the transistor M15 and a gate-to-source voltage Vgs9 of the transistor M9, i.e. Vgs11+Vgs12=Vgs9+Vgs15. Therefore, by matching the transistors M9, M12 to make the gate-to-source voltage Vgs12 equal to the gate-to-source voltage Vgs9, i.e. Vgs12=Vgs9, the gate-to-source voltage Vgs11 can be equal to the gate-to-source voltage Vgs15, i.e. Vgs11=Vgs15. A current Id of a transistor is generally expressed as follows:
                              Id          =                                    1              2                        ⁢                          μ              n                        ⁢            Cox            ⁢                          W              L                        ⁢                                          (                                  Vgs                  -                                      V                    T                                                  )                            2                        ⁢                          (                              1                +                                  λ                  ⁢                                                                          ⁢                  Vds                                            )                                      ,                            (                  Eq          .                                          ⁢          1                )            
Eq. 1 can be rewritten as follows:
                              Vgs          =                                    V              T                        +                                                            2                  ⁢                  Id                                                                      μ                    n                                    ⁢                  Cox                  ⁢                                      W                    L                                    ⁢                                      (                                          1                      +                                              λ                        ⁢                                                                                                  ⁢                        Vds                                                              )                                                                                      ,                            (                  Eq          .                                          ⁢          2                )            
Since the gate-to-source voltage Vgs11 is equal to the gate-to-source voltage Vgs15, a relation between the output stage quiescent current IQ and the bias current IB2 can be expressed as follows:
                                                        IQ                                                                    (                                          W                      L                                        )                                    15                                ⁢                                  (                                      1                    +                                          λ                      ⁢                                                                                          ⁢                      Vds                      ⁢                                                                                          ⁢                      15                                                        )                                                              =                                                                      IB                  ⁢                                                                          ⁢                  2                                                                                            (                                              W                        L                                            )                                        11                                    ⁢                                      (                                          1                      +                                              λ                        ⁢                                                                                                  ⁢                        Vds                        ⁢                                                                                                  ⁢                        11                                                              )                                                              ⁢                                                                                  ,                            (                  Eq          .                                          ⁢          3                )            
Eq. 3 can be rewritten as follows:
                              IQ          =                                                                                          (                                          W                      L                                        )                                    15                                ⁢                                  (                                      1                    +                                          λ                      ⁢                                                                                          ⁢                      Vds                      ⁢                                                                                          ⁢                      15                                                        )                                                                                                  (                                          W                      L                                        )                                    11                                ⁢                                  (                                      1                    +                                          λ                      ⁢                                                                                          ⁢                      Vds                      ⁢                                                                                          ⁢                      11                                                        )                                                      ⁢            IB            ⁢                                                  ⁢            2                          ,                            (                  Eq          .                                          ⁢          4                )            
As can be seen from Eq. 4, if no signal is inputted into the input terminals Vin−, Vin+, i.e. a quiescent operating status, a ratio of the output stage quiescent current IQ to the bias current IB2 is substantially equal to a ratio of a W/L ratio (W/L)15 of the transistor M15 to a W/L ratio (W/L)11 of the transistor M11, i.e. the output stage quiescent current IQ is proportional to the bias current IB2.
However, in practical operations, if a lower bias current IB2 is applied for reducing power consumption of the class AB OP 10 in the quiescent operating status, efficiency of the class AB OP 10 in a dynamic operating status (signals are inputted into the input terminals Vin−, Vin+) is also reduced; and if a higher bias current IB2 is applied for enhancing the efficiency of the class AB OP 10 in the dynamic operating status, the power consumption of the class AB OP 10 in the quiescent operating status is also increased. Thus, there is a need for improvement of the prior art.